1. Field of the Invention
This invention relates to the improvement of a nonvolatile semiconductor memory, and more particularly to the improvement of a stress test circuit for effecting the stress test by applying a stress test voltage to memory cell transistors of a nonvolatile semiconductor memory.
2. Description of the Related Art
In general, memory cells of a nonvolatile semiconductor memory, for example, memory cells of an EPROM in which data can be erased by application of ultraviolet rays and data can be programmed again are each formed of a transistor having a control gate and a floating gate formed with the double layered structure on a semiconductor substrate. In such a semiconductor memory, the source of the memory cell transistor is kept at the ground potential and programming voltage Vpp of high voltage level is applied to the word line and the bit line respectively connected to the control gate and drain of the memory cell transistor in order to program data into the memory cell. In the memory cell to be programmed, a high voltage is applied to the drain thereof to set up a strong electric field in that portion of the channel region which lies near the drain. As a result, hot electrons are generated and then injected into the floating gate by an electric field set up by a high voltage applied to the control gate. The threshold voltage of a memory cell transistor in which electrons are injected into the floating gate becomes high in comparison with that of a memory cell transistor in which no electrons are injected into the floating gate, and in this way data can be programmed.
FIG. 1 shows an arrangement of part of the prior art EPROM. As shown in FIG. 1, common bit lines BLa to BLb are serially connected to transistors 1 to 2 for selecting the common bit lines, and each of common bit lines BLa to BLb is commonly connected to m bit lines or m column lines BLl to BLm which are in turn connected in series with transistors 3 to 4 for selecting bit lines BLl to BLm. Further, transistors 1 to 2 are commonly connected to programming power source voltage Vpp via programming transistor 7 which has a control signal VPGM applied to its gate. Memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm) formed of floating gate type transistors are arranged in the matrix form, the drains thereof being connected to respective bit lines BLl to BLm, the control gates thereof being connected to the respective word lines or row lines WLl to WLn, and the sources thereof being connected to the ground lines (not shown).
Assume now that data is programmed into one of the memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm), for example, memory cell Mll in the programming mode of the above semiconductor memory. In this case, word line WLl is selected by row decoder 6 and is supplied with a high voltage. At the same time, transistor 7 is turned on and transistors 1 and 3 are respectively turned on by decoders 5-1 and 5-2 so as to select common bit line BLa. As a result, a high voltage serving as the programming voltage is supplied via selected bit line BLa. Thus, electrons are injected into the floating gate of the floating gate type transistor constituting memory cell Mll, thereby programming data into memory cell Mll.
In a case where data is written or programmed into memory cell Mll, (n-1) memory cells M21 to Mnl except memory cell Mll are all kept in the nonselective condition. At this time, the control gates of the transistors constituting memory cells M21 to Mnl are kept at the ground potential, and a high voltage is applied as electrical stress to the drains of the transistors constituting memory cells M21 to Mnl. If there is any deficiency in the data storing and holding function of the transistors constituting memory cells M21 to Mnl, for example, if a transistor in which data has been programmed has an excessively thin or defective gate insulation film, then electrons are emitted from the floating gate of the transistor when the high programming voltage is applied as the electrical stress to the drain of the transistor, thus causing the stored data to be erased.
In general, in the above semiconductor memory, a test for reliability or stress test is effected to check the data holding characteristics of semiconductor memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm). In the stress test, after data is programmed into all the semiconductor memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm), word lines WLl to WLn are kept in the non-selection state, and bit lines BLl to BLm are selected and set to a high programming voltage. After this, data is read out from each of semiconductor memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm) and a memory cell or memory cells having defective stored data holding function are detected based on the readout data. During the stress test, a high programming voltage is sequentially applied to the bit lines to read out data from the memory cells in the memory having column decoders 5-1 and 5-2 to which N-bit address is supplied. Therefore, it takes a long time for the stress test.
A stress test method for reducing the test period is proposed in which all the bit lines BLl to BLm are selected by column decoders 5-1 and 5-2 and a high programming voltage is applied to all the bit lines BLl to BLm while word lines WLl to WLn are kept in the non-selection state in the test mode. In the stress test method, high voltage Vpp is applied to turn on transistor 7 as shown in FIG. 2. At the same time, high voltage Vpp is generated from column decoders 5-1 and 5-2 to turn on transistors 1, 3 and 7, thus selecting bit lines BLl to BLm. Further, clamp circuit 8 which is connected to connection node A between transistor 7 and bit lines BLl to BLm and is used to set connection node A to a programming voltage is operated so as to cause a test voltage of the same level as the programming voltage to be applied to the drains of those semiconductor memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm) which are kept in the non-selected state. After the test voltage is applied, data recording states of memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm) are checked.
According to the above test method, the test voltage can be efficiently applied to memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm). However, it has the following problem. That is, as shown in FIG. 3, if there is defective portion 9 causing current to leak between a bit line, for example, bit line BLm and the ground line, or if the bit line is defective, a transistor constituting the memory cell is defective, or defective contact occurs between the bit line and the word line, then a current leak path of connection node A, transistor 1, connection node B, transistor 4 and defective portion 9 is formed. As a result, potential at connection node B is lowered and potential at connection node A is also lowered. Therefore, it becomes impossible to apply a test voltage of the same level as the programming voltage to memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm). In this case, it is only possible to apply a voltage lower than the test voltage, and a satisfactory test cannot be effected. If it is only possible to apply a voltage lower than the test voltage to memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm), memories having a defective stored data holding function cannot be correctly detected in the stress test even if they are included in the memory cells (Mll, . . . , Mnl), (Mlm, . . . , Mnm).
The bit line in which defective portion 9 tends to occur is detected in the test operation other than the stress test, and can be compensated for by use of a redundancy circuit. However, the stress test is influenced by the bit line having defective portion 9, making it impossible to detect the defective memory cells. Therefore, there is a possibility that the semiconductor memory including the defective memory cells is sold on the market.